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? semiconductor components industries, llc, 2015 november, 2016 ? rev. 4 1 publication order number: kai?16070/d kai-16070 4864 (h) x 3232 (v) interline ccd image sensor descriptio n the kai?16070 image sensor is a 16?megapixel ccd in a 35 mm optical format. based on the truesense 7.4 micron interline transfer ccd platform, the sensor provides very high smear rejection and up to 82 db linear dynamic range through the use of a unique dual?gain amplifier. flexible readout architecture enables use of 1, 2, or 4 outputs for full resolution readout up to 8 frames per second, while a vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. the sensor is available with the truesense sparse color filter pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color bayer part. the sensor shares common pin?out and electrical configurations with a full family of on semiconductor interline transfer ccd image sensors, allowing a single camera design to be leveraged in support of multiple devices. table 1. general specifications parameter typical value architecture interline ccd; progressive scan total number of pixels 4932 (h) x 3300 (v) number of effective pixels 4888 (h) x 3256 (v) number of active pixels 4864 (h) x 3232 (v) (15.7 m) pixel size 7.4 m (h) x 7.4 m (v) active image size 36.0 mm (h) x 23.9 mm (v) 43.2 mm (diag.) 35 mm optical format aspect ratio 3:2 number of outputs 1, 2, or 4 charge capacity 44,000 electrons output sensitivity 9.7 v/e ? (low), 33 v/e ? (high) quantum efficiency mono (?aaa) mono (?axa, ?pxa, ?qxa) r, g, b (?cxa) r, g, b (?fxa) 10% 48% 32%, 41%, 39% 33%, 40%, 40% base iso ?axa ?cxa, ?pxa ?fxa, ?pxa 350 130, 310 (respectively) 130, 310 (respectively) read noise (f = 40 mhz) 12 electrons rms dark current photodiode / vccd 1 / 145 electrons/s dark current doubling temp. photodiode / vccd 7 c / 9 c dynamic range high gain amp (40 mhz) dual amp, 2x2 bin (40 mhz) 70 db 82 db charge transfer efficiency 0.999999 blooming suppression > 1000 x smear ?115 db image lag < 10 electrons maximum pixel clock speed 40 mhz maximum frame rates quad / dual / single output 8 / 4 / 2 fps package 72 pin pga cover glass ar coated, 2 sides or clear glass note: all parameters are specified at t = 40 c unless otherwise noted. www.onsemi.com figure 1. kai?16070 ccd image sensor features ? superior smear rejection ? up to 82 db linear dynamic range ? bayer color pattern, truesense spars e color filter pattern, and monochrome configurations ? progressive scan & flexible readout architecture ? high frame rate ? high sensitivity ? low noise architectur e ? package pin reserved for device identification applications ? industrial imaging and inspection ? traffic ? aerial photography see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kai?16070 www.onsemi.com 2 ordering information table 2. ordering information part number description marking code kai?16070?aaa?jp?b1 monochrome, no microlens, pga package, taped clear cover glass, no coatings, standard grade kai?16070?aaa serial number kai?16070?aaa?jp?ae monochrome, no microlens, pga package, taped clear cover serial number glass, no coatings, engineering grade kai?16070?axa?jd?b1 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai?16070?axa serial number kai?16070?axa?jd?b2 monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai?16070?axa?jd?ae monochrome, special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai?16070?fxa?jd?b1 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai?16070?fxa serial number kai?16070?fxa?jd?b2 gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai?16070?fxa?jd?ae gen2 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai?16070?qxa?jd?b1 gen2 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai?16070?qxa serial number kai?16070?qxa?jd?b2 gen2 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai?16070?qxa?jd?ae gen2 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai?16070?cxa?jd?b1* gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai?16070?cxa serial number kai?16070?cxa?jd?b2* gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai?16070?cxa?jd?ae* gen1 color (bayer rgb), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai?16070?pxa?jd?b1* gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 1 kai?16070?pxa serial number kai?16070?pxa?jd?b2* gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), grade 2 kai?16070?pxa?jd?ae* gen1 color (truesense sparse cfa), special microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade *not recommended for new designs. see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
kai?16070 www.onsemi.com 3 device description architecture figure 2. block diagram 22 dark 22 v1b 12 buffer 12 12 22 m x 7.4 m pixels 2432 2432 2432 2432 (last vccd phase = v1 h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 12 22 12 devid 10 1 fdgab fdgab f dgcd f dgcd r2cd r2ab r2cd r2ab dark reference pixels there are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. the dark rows are not entirely dark and so should not be used for a dark reference level. use the 22 dark columns on the left or right side of the image sensor as a dark reference. under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. dummy pixels within each horizontal shift register there are 11 leading additional shift phases. these pixels are designated as dummy pixels and should not be used to determine a dark reference level. in addition, there is one dummy row of pixels at the top and bottom of the image. active buffer pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non?uniformities. image acquisitio n an electronic representation of an image is formed when incident photons falling on the sensor plane create electron?hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non?linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming.
kai?16070 www.onsemi.com 4 esd protection adherence to the power?up and power?down sequence is critical. failure to follow the proper power?up and power?down sequences may cause damage to the sensor. see power?up and power?down sequence section. bayer color filter pattern figure 3. bayer color filter pattern 22 dark 22 v1b 12 buffer 12 12 b g g r 22 fld fld 4864h x 3232v 7.4 m x 7.4 m pixels 2432 2432 2432 2432 (last vccd phase = v1 h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 22 12 devid b g g r b g g r b g g r fdgab fdgab f dgcd f dgcd r2cd r2ab r2cd r2ab 22 dark 22 v1b 12 buffer 12 12 b g g r 22 fld fld 4864h x 3232v 7.4 m x 7.4 m pixels 2432 2432 2432 2432 (last vccd phase = v1 h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 22 12 devid b g g r b g g r b g g r fdgab fdgab f dgcd f dgcd r2cd r2ab r2cd r2ab truesense sparse color filter pattern figure 4. truesense sparse color filter pattern 22 dark 22 v1b 12 buffer 12 12 22 fld fld 4864h x 3232v 7.4 m x 7.4 m pixels 2432 2432 2432 2432 (last vccd phase = v1 h1s) v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 8 22 10 1 12 22 12 devid p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p p b g r p b p p g g g p p p r p fdgab fdgab f dgcd f dgcd r2cd r2ab r2cd r2ab
kai?16070 www.onsemi.com 5 physical description pin description and device orientation figure 5. package pin designations ? top view 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 v3b pixel (1,1) v3b v1b v1b vdda vddb gnd ra gnd rb h2sla h2slb h1ba h1bb h2sa h2sb sub r2ab v3t v3t v1t v1t vddc vddd gnd rc gnd rd h2slc h2sld h1bc h1bd h2sc h2sd r2cd sub v4b esd v4b v2b v2b vouta voutb rda rdb oga ogb h2ba h2bb h1sa h1sb fdgab fdgab v4t devid v4t v2t v2t voutc voutd rdc rdd ogc ogd h2bc h2bd h1sc h1sd fdgcd fdgcd esd
kai?16070 www.onsemi.com 6 table 3. pin description pin name description 1 v3b vertical ccd clock, phase 3, bottom [2] [no pin ? keyed] 3 v1b vertical ccd clock, phase 1, bottom 4 v4b vertical ccd clock, phase 4, bottom 5 vdda output amplifier supply, quadrant a 6 v2b vertical ccd clock, phase 2, bottom 7 gnd ground 8 vouta video output, quadrant a 9 ra reset gate, standard (high) gain, quadrant a 10 rda reset drain, quadrant a 11 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 12 oga output gate, quadrant a 13 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 14 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 15 h2sa horizontal ccd clock, phase 2, storage, quadrant a 16 h1sa horizontal ccd clock, phase 1, storage, quadrant a 17 sub substrate 18 fdgab fast line dump gate, bottom 19 r2ab reset gate, low gain, quadrants a & b 20 fdgab fast line dump gate, bottom 21 h2sb horizontal ccd clock, phase 2, storage, quadrant b 22 h1sb horizontal ccd clock, phase 1, storage, quadrant b 23 h1bb horizontal ccd clock, phase 1, barrier, quadrant b 24 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 25 h2slb horizontal ccd clock, phase 2, storage, last phase, quadrant b 26 ogb output gate, quadrant b 27 rb reset gate, standard (high) gain, quadrant b 28 rdb reset drain, quadrant b 29 gnd ground 30 voutb video output, quadrant b 31 vddb output amplifier supply, quadrant b 32 v2b vertical ccd clock, phase 2, bottom 33 v1b vertical ccd clock, phase 1, bottom 34 v4b vertical ccd clock, phase 4, bottom 35 v3b vertical ccd clock, phase 3, bottom 36 esd esd protection disable pin name description 72 esd esd protection disable 71 v3t vertical ccd clock, phase 3, top 70 v4t vertical ccd clock, phase 4, top 69 v1t vertical ccd clock, phase 1, top 68 v2t vertical ccd clock, phase 2, top 67 vddc output amplifier supply, quadrant c 66 voutc video output, quadrant c 65 gnd ground 64 rdc reset drain, quadrant c 63 rc reset gate, standard (high) gain, quadrant c 62 ogc output gate, quadrant c 61 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 60 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 59 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 58 h1sc horizontal ccd clock, phase 1, storage, quadrant c 57 h2sc horizontal ccd clock, phase 2, storage, quadrant c 56 fdgcd fast line dump gate, top 55 r2cd reset gate, low gain, quadrants c & d 54 fdgcd fast line dump gate, top 53 sub substrate 52 h1sd horizontal ccd clock, phase 1, storage, quadrant d 51 h2sd horizontal ccd clock, phase 2, storage, quadrant d 50 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 49 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 48 ogd output gate, quadrant d 47 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 46 rdd reset drain, quadrant d 45 rd reset gate, standard (high) gain, quadrant d 44 voutd video output, quadrant d 43 gnd ground 42 v2t vertical ccd clock, phase 2, top 41 vddd output amplifier supply, quadrant d 40 v4t vertical ccd clock, phase 4, top 39 v1t vertical ccd clock, phase 1, top 38 devid device identification 37 v3t vertical ccd clock, phase 3, top 1. liked named pins are inter nally connected and should have a common drive signal.
kai?16070 www.onsemi.com 7 imaging performance table 4. typical operation conditions unless otherwise noted, the imaging performance specifications are measured using the following conditions. description condition notes light source continuous red, green and blue led illumination for monochrome sensor, only green led used. operation nominal operating voltages and timing table 5. specifications ? all configurations description symbol min. nom. max. units sam- pling plan temperature tested at ( c) notes dark field global non?uniformity dsnu ? ? 5 mvpp die 27, 40 bright field global non?uniformity ? 2 12 %rms die 27, 40 1 bright field global peak to peak non? uniformity prnu ? 10 30 %pp die 27, 40 1 bright field center non?uniformity ? 1 2 %rms die 27, 40 1 maximum photo?response nonlinearity high gain (4,000 to 20,000 electrons) high gain (4,000 to 40,000 electrons) low gain (8,000 to 80,000 electrons) nl_hg1 nl_hg2 nl_lg1 ? ? ? 2 3 6 ? ? ? % design 2 maximum gain difference between outputs g ? 10 ? % design 2 horizontal ccd charge capacity hne ? 90 ? ke ? design vertical ccd charge capacity vne ? 60 ? ke ? design photodiode charge capacity pne ? 44 ? ke ? die 27, 40 3 floating diffusion capacity ? high gain fne_hg 40 ? ? ke ? die 27, 40 floating diffusion capacity ? low gain fne_lg 160 ? ? ke ? die 27, 40 linear saturation level ? high gain lsat_hg ? 40 ? ke ? design linear saturation level ? low gain lsat_lg ? 160 ? ke ? design horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current ipd ? 2 70 e/p/s die 40 vertical ccd dark current ivd ? 200 600 e/p/s die 40 image lag lag ? ? 10 e ? design antiblooming factor xab 1000 ? ? design vertical smear smr ? ?115 ? db design read noise (high gain / low gain) n e?t ? 12 / 45 ? e ? rms design 4 dynamic range, standard dr ? 70.5 ? db design 4, 5 dynamic range, extended linear dynamic range mode (xldr) xldr ? 82.5 ? db design 4, 5 output amplifier dc offset v odc 5 9.0 14 v die 27, 40 output amplifier bandwidth f ?3db ? 250 ? mhz design 6 output amplifier impedance r out 100 127 200 die 27, 40 output amplifier sensitivity high gain low gain v/ n ? ? 33 9.7 ? ? v/e ? design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is 1450 mv. this value is determined while operating the device in the low gain mode. vab level assigned is val id for both modes; high gain or low gain. 4. at 40 mhz 5. uses 20log (pne/ n e?t ) 6. assumes 5 pf load.
kai?16070 www.onsemi.com 8 table 6. kai?16070?aaa configuration with no glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency qe max ? 10 ? % design 1 peak quantum efficiency wavelength qe ? 500 ? nm design 1 1. measurement taken without cover glass. table 7. kai?16070?axa, kai?16070?pxa, and kai?16070?qxa configurations description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency qe max ? 48 ? % design peak quantum efficiency wavelength qe ? 500 ? nm design 1. this color filter set configuration (gen1) is not recommended for new designs. table 8. kai?16070?fxa and kai?16070?qxa gen2 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 40 40 34 ? % design peak quantum efficiency wavelength blue green red qe ? 460 535 605 ? nm design table 9. kai?16070?cxa and kai?16070?pxa gen1 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 39 41 32 ? % design 1 peak quantum efficiency wavelength blue green red qe ? 470 540 620 ? nm design 1 1. this color filter set configuration (gen1) is not recommended for new designs.
kai?16070 www.onsemi.com 9 linear signal range high gain figure 6. high gain linear signal range output of sensor not verified or guaranteed 40,000 0 0 output signal (electrons) light or exposure (arbitrary) 20,000 30,000 10,000 1,320 output signal (mv) 990 660 330 0 4,000 132 linearity guaranteed to 2% linearity guaranteed to 3% low gain figure 7. low gain linear signal range output of sensor not verified or guaranteed 160,000 0 0 output signal (electrons) light or exposure (arbitrary) 80,000 120,000 40,000 1,600 output signal (mv) 1,200 800 400 0 8,000 80 linearity guaranteed to 6%
kai?16070 www.onsemi.com 10 typical performance curves quantum efficiency monochrome without microlens figure 8. monochrome without microlens quantum efficiency monochrome with microlens figure 9. monochrome with microlens quantum efficiency
kai?16070 www.onsemi.com 11 color (bayer rgb) with microlens (gen2 and gen1 cfa) figure 10. color (bayer) with microlens quantum efficiency color (truesense sparse cfa) with microlens (gen2 and gen1 cfa) figure 11. color (truesense sparse cfa) with microlens quantum efficiency
kai?16070 www.onsemi.com 12 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?v ertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 12. monochrome with microlens angular quantum efficiency 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40?30?20?10 0 10 20 30 40 normalized quantum efficiency angle (degrees) horizontal vertical dark current versus temperature figure 13. dark current versus temperature 0.010 0.100 1.000 10.000 100.000 1000.000 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 dark current (e/s) 1000/ t(k) pd vccd 70 c 60 c 50 c 40 c 30 c 20 c 10 c
kai?16070 www.onsemi.com 13 power ? estimated figure 14. power
kai?16070 www.onsemi.com 14 frame rates figure 15. frame rates
kai?16070 www.onsemi.com 15 defect definitions table 10. operation conditions for defect testing at 40 c description condition notes operational mode one output using vouta, continuous readout hccd clock frequency 20 mhz pixels per line 5000 1 lines per frame 3354 2 line time 266 sec frame time 894 msec photodiode integration time pd_tint = frame time = 894 msec, no electronic shutter used temperature 40 c light source continuous red, green and blue led illumination 3 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. for monochrome sensor, only the green led is used. table 11. defect definitions for testing at 40 c description definition grade 1 grade 2 mono grade 2 color notes major dark field defective bright pixel pd_tint = frame time; defect 325 mv 150 300 300 1 major bright field defective dark pixel defect 15% minor dark field defective bright pixel pd_tint = frame time; defect 163 mv 1500 3000 3000 cluster defect a group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally. 30 30 30 2 column defect a group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 1. for the color devices (kai?16070?fxa, kai?16070?qxa, kai?16070?cxa, and kai?16070?pxa), a bright field defective pixel deviat es by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). 3. tested at 40 c with no electronic shutter used.
kai?16070 www.onsemi.com 16 table 12. operation conditions for defect testing at 27 c description condition notes operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 20 mhz pixels per line 5000 1 lines per frame 3354 2 line time 266 sec frame time 894 msec photodiode integration time (pd_tint) pd_tint = frame time = 894 msec, no electronic shutter used temperature 27 c light source continuous red, green and blue led illumination 3 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. for monochrome sensor, only the green led is used. table 13. defect definitions for testing at 27 c description definition grade 1 grade 2 mono grade 2 color notes major dark field defective bright pixel pd_tint = frame time defect 100 mv 150 300 300 1 major bright field defective dark pixel defect 15% minor dark field defective bright pixel pd_tint = frame time; defect 52 mv 1500 3000 3000 cluster defect a group of 2 to 19 contiguous major defective pixels, but no more than 4 adjacent defects horizontally. 30 30 30 2 column defect a group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 1. for the color devices (kai?16070?fxa, kai?16070?qxa, kai?16070?cxa, and kai?16070?pxa), a bright field defective pixel deviat es by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). 3. tested at 27 c with no electronic shutter used. 4. defectivity levels for a unit with the taped cover glass configuration (non?sealed cover glass) of this device cannot be guaranteed after f inal testing at the factory. image sensors are tested for defects and are mapped prior to shipment. additional pixel defects and clu sters may appear for devices purchased without a sealed cover glass. defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps. see figure 16: regions of interest for the location of pixel 1,1.
kai?16070 www.onsemi.com 17 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (4888, 3256) active area roi: pixel (13, 13) to pixel (4876, 3244) center roi: pixel (2345, 1527) to pixel (2444, 1628) only the active area roi pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 16 for a pictorial representation of the regions of interest. figure 16. regions of interest horizontal overclock 12 buffer rows 12 buffer rows 12 buffer columns 12 buffer columns 22 dark columns 22 dark columns 12 dark rows vouta 12 dark rows 4864 (h) x 3232 (v) active pixels 1, 1 13, 13 pixel pixel voutc
kai?16070 www.onsemi.com 18 tests dark field global non?uniformity this test is performed under dark field conditions. the sensor is partitioned into 1 mm x 1 mm sub regions, each of which is 135 by 135 pixels in size. the average signal level of each of the sub regions of interest is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] = (roi average in counts ? horizontal overclock average in counts) * mv per count where i = 1 to total # of sub regions. during this calculation on the sub regions of interest, the maximum and minimum signal levels are found. the dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. units: mvpp (millivolts peak to peak) global non?uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1320 mv . global non?uniformity is defined as globalnon?uniformity 100 activeareastandarddeviation activeareasignal units: %rms. active area signal = active area average ? dark column average global peak to peak non?uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1320 mv. the sensor is partitioned into sub regions of interest, each of which is 135 by 135 pixels in size. the average signal level of each of the before mentioned sub regions of interest (roi) is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] = (roi average in counts ? horizontal overclock average in counts) * mv per count where i = 1 to total # of sub regions. during this calculation on the sub regions of interest, the maximum and minimum signal levels are found. the global peak to peak uniformity is then calculated as: globaluniformity 100 maximumsignal minimumsignal activeareasignal units: %pp center non?uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 924 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1320 mv. defects are excluded for the calculation of this test. this test is performed on the center 100 by 100 pixels of the sensor. center uniformity is defined as: center roi uniformity 100 center roi standard deviation center roi signal units: %rms. center roi signal = center roi average ? dark column average dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 1 mm x 1 mm sub regions, each of which is 135 by 135 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?defect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 924 mv. prior to this test being performed the substrate voltage has been set such that the char ge capacity of the sensor is 1320 mv. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal * threshold bright defect threshold = active area signal * threshold the sensor is then partitioned into 1 mm x 1 mm sub regions of interest, each of which is 135 by 135 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified.
kai?16070 www.onsemi.com 19 example for major bright field defective pixels: ? average value of all active pixels is found to be 924 mv ? dark defect threshold: 924 mv * 15% = 138 mv ? bright defect threshold: 924 mv * 15% = 138 mv ? region of interest #1 selected. this region of interest is pixels 13, 13 to pixels 147, 147. ? median of this region of interest is found to be 918 mv. ? any pixel in this region of interest that is (918 + 138 mv) 1062 mv in intensity will be marked defective. ? any pixel in this region of interest that is (918 ? 138 mv) 780 mv in intensity will be marked defective. ? all remaining sub regions of interest are analyzed for defective pixels in the same manner. any remaining factor of pixels less than 135 pixels that are not covered by this moving roi is placed over the remaining pixels at the active area boundary. a portion of pixels that were tested in the previous roi will be retested to keep the test roi at a full 135 by 135 pixels.
kai?16070 www.onsemi.com 20 operation table 14. absolute maximum ratings description symbol minimum maximum units notes operating temperature t op ?50 +70 c 1 humidity rh +5 +90 % 2 output bias current i out 60 ma 3 off?chip load c l 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ?15 ma for each output. avoid shorting output pins to ground or any low impedance s ource during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 15. absolute maximum voltage ratings between pins and ground description minimum maximum units notes vdd , vout ?0.4 17.5 v 1 rd ?0.4 15.5 v 1 v1b, v1t esd ? 0.4 esd + 24.0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v fdgab, fdgcd esd ? 0.4 esd + 14.0 v h1s , h1b , h2s , h2b , h2sl , r , og esd ? 0.4 esd + 14.0 v 1 esd ?10.0 0.0 v sub ?0.4 +40.0 v 2 1. denotes a, b, c or d 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. kai?29050 compatibility the kai?16070 is pin?for?pin compatible with a camera designed for the kai?29050 image sensor with the following accommodations: 1. to operate in accordance with a system designed for kai?29050, the target substrate voltage should be set to be 2.0 v higher than the value recorded on the kai?16070 shipping container. this setting will cause the charge capacity to be limited to 20 ke ? (or 660 mv). 2. on the kai?16070, pins 19 (r2ab) and 55 (r2cd) should be left floating per the kai?29050 device performance specification. 3. the kai?16070 will operate in only the high gain mode (33 v/e). 4. all timing and voltages are taken from the kai?29050 specification sheet. 5. the number of horizontal and vertical ccd clock cycles is reduced as appropriate. 6. in addition, if the intent is to operate the kai?16070 image sensor in a camera designed for the kai?29050 sensor that has been modified to accept and process the full 40,000 e ? (1,320 mv) output, the following changes to the following voltage bias must be made: voltage bias differences kai?29050 kai?16070 pins 10, 28, 46, and 64 12.0 v per the specification increase this value to 12.6 v note: to make use of the low gain mode or dual gain mode the kai?16070 voltages and timing specification must be used.
kai?16070 www.onsemi.com 21 reset pin, low gain (r2ab and r2cd) the r2ab and r2bc (pins 19 and 55) each have an internal circuit to bias the pins to 4.3 v. this feature assures the device is set to operate in the high gain mode when pins 19 and 55 are not connected in the application to a clock driver (for kai?29050 compatibility). typical capacitor coupled drivers will not drive this structure. figure 17. equivalent circuit for reset gate, low gain (r2ab and r2cd) gnd vdd (+15 v) r2 4.3 v vdd (+15 v) 27 k 20 k 68 k gnd 27 k 20 k 68 k
kai?16070 www.onsemi.com 22 power?up and power?down sequence adherence to the power?up and power?down sequence is critical. failure to follow the proper power?up and power?down sequences may cause damage to the sensor. figure 18. power?up and power?down sequence vdd sub esd vccd low hccd low time v+ v? activate all other biases when esd is stable and sub is above 3v do not pulse the electronic shutter until esd is stable notes: 7. activate all other biases when esd is stable and sub is above 3 v 8. do not pulse the electronic shutter until esd is stable 9. vdd cannot be +15 v when sub is 0 v 10. the image sensor can be protected from an accidental improper esd voltage by current limiting the sub current to less than 10 ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and ground will protect the sensor from accidental overshoots of sub, vdd and esd during power on and power off. see the figure below. the vccd clock waveform must not have a negative overshoot more than 0.4 v below the esd voltage. figure 19. all vccd and fdg clocks absolute maximum overshoot of 0.4 v 0.0v esd esd ? 0.4v example of external diode protection for sub, vdd and esd. denotes a, b, c or d figure 20. gnd sub vdd esd
kai?16070 www.onsemi.com 23 table 16. dc bias operating conditions description pins symbol minimum nominal maximum units maximum dc current notes reset drain rd rd +12.4 +12.6 +12.8 v 10 a 1, 9 output gate og og ?2.2 ?2.0 ?1.8 v 10 a 1 output amplifier supply vdd vdd +14.5 +15.0 +15.5 v 11.0 ma 1,2 ground gnd gnd 0.0 0.0 0.0 v ?1.0 ma substrate sub vsub +5.0 vab vdd v 50 a 3, 8 esd protection disable esd esd ?9.5 ?9.0 vx_l v 50 a 6, 7, 10 output bias current vout iout ?3.0 ?5.0 ?10.0 ma 1, 4, 5 1. denotes a, b, c or d 2. the maximum dc current is for one output. idd = iout + iss. see figure 21. 3. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is the nominal pne (see specifications). 4. an output load sink must be applied to each vout pin to activate each output amplifier. 5. nominal value required for 40 mhz operation per output. may be reduced for slower data rates and lower noise. 6. adherence to the power?up and power?down sequence is critical. see power?up and power?down sequence section. 7. esd maximum value must be less than or equal to v1_l + 0.4 v and v2_l + 0.4 v 8. refer to application note using interline ccd image sensors in high intensity visible lighting conditions 9. 12.0 v may be used if the total output signal desired is 20,000 e ? or less. 10. where vx_l is the level set for v1_l, v2_l, v3_l, or v4_l in the application. figure 21. output amplifier ? showing dual reset pins floating diffusion source follower #1 source follower #2 source follower #3 iout idd iss hccd r2 rd vdd og vout r
kai?16070 www.onsemi.com 24 ac operating conditions table 17. clock levels description pins symbol level minimum nominal maximum units vertical ccd clock, phase 1 v1b, v1t 1 v1_l low ?8.2 ?8.0 ?7.8 v v1_m mid ?0.2 0.0 +0.2 v1_h high +12.8 +13.0 +14.0 vertical ccd clock, phase 2 v2b, v2t 1 v2_l low ?8.2 ?8.0 ?7.8 v v2_h high ?0.2 0.0 +0.2 vertical ccd clock, phase 3 v3b, v3t 1 v3_l low ?8.2 ?8.0 ?7.8 v v3_h high ?0.2 0.0 +0.2 vertical ccd clock, phase 4 v4b, v4t 1 v4_l low ?8.2 ?8.0 ?7.8 v v4_h high ?0.2 0.0 +0.2 horizontal ccd clock, phase 1 storage h1s 1 h1s_l low ?5.0 (5) ?4.4 ?4.2 v h1s_a amplitude +4.2 +4.4 +5.0 (5) horizontal ccd clock, phase 1 barrier h1b 1 h1b_l low ?5.0 (5) ?4.4 ?4.2 v h1b_a amplitude +4.2 +4.4 +5.0 (5) horizontal ccd clock, phase 2 storage h2s 1 h2s_l low ?5.0 (5) ?4.4 ?4.2 v h2s_a amplitude +4.2 +4.4 +5.0 (5) horizontal ccd clock, phase 2 barrier h2b 1 h2b_l low ?5.0 (5) ?4.4 ?4.2 v h2b_a amplitude +4.2 +4.4 +5.0 (5) horizontal ccd clock, last phase 2 h2sl 1 h2sl_l low ?5.2 ?5.0 ?4.8 v h2sl_a amplitude +4.8 +5.0 +5.2 reset gate r 1 r_l 3 low ?3.2 ?3.0 ?2.8 v r_a amplitude +6.0 +6.4 reset gate r2ab, r2cd r_l 3 low ?2.0 ?1.8 ?1.6 v r_a amplitude +6.0 +6.4 electronic shutter 4 sub ves high +29.0 +30.0 +40.0 v fast line dump gate fdg 1 fdg_l low ?8.2 ?8.0 ?7.8 v fdg_h high +4.5 +5.0 +5.5 1. denotes a, b, c or d 2. use separate clock driver for improved speed performance. 3. reset low should be set to ?3 volts for signal levels greater than 40,000 electrons. 4. refer to application note using interline ccd image sensors in high intensity visible lighting conditions 5. if the minimum horizontal clock low level is used (?5.0 v), then the maximum horizontal clock amplitude should be used (5 v a mplitude) to create a ?5.0 v to 0.0 v clock. the figure below shows the dc bias (vsub) and ac clock (ves) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 22. vsub ves gnd gnd
kai?16070 www.onsemi.com 25 capacitance table 18. capacitance v1b v2b v3b v4b v1t v2t v3t v4t gnd all pins units v1b x 17 11 14 6 5 6 4 24 88 nf v2b x x 21 10 5 3 4 3 7 74 nf v3b x x x 19 6 5 6 4 8 83 nf v4b x x x x 5 4 5 3 23 76 nf v1t x x x x x 14 11 17 24 86 nf v2t x x x x x x 16 6 22 75 nf v3t x x x x x x x 19 11 84 nf v4t x x x x x x x x 5 73 nf fdgt 0.6 0.5 0.5 0.4 16 3.1 1.0 1.1 94 117 pf fdgb 0.6 0.5 0.5 0.4 16 3.1 1.0 1.1 94 117 pf vsub 2 2 2 2 2 2 2 2 11 11 nf h2s h1b h2b gnd all pins units h1s 45 75 44 196 360 pf h2s x 47 41 281 368 pf h1b x x 12 313 324 pf h2b x x x 293 293 pf 1. tables show typical cross capacitance between pins of the device. 2. capacitance is total for all like named pins.
kai?16070 www.onsemi.com 26 device identification the device identification pin (devid) may be used to identify different members of the on semiconductor 5.5 micron and 7.4 micron interline transfer ccd platforms. table 19. device identification description pins symbol minimum nominal maximum units maximum dc current notes device identification devid devid 32,000 40,000 48,000 50 a 1, 2, 3 1. nominal value subject to verification and/or change during release of preliminary specifications. 2. if the device identification is not used, it may be left disconnected. 3. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit note that v1 must be a different value than v2. figure 23. device identification recommended circuit adc r_external v1 v2 devid gnd kai?16070 r_deviceid
kai?16070 www.onsemi.com 27 timing table 20. requirements and characteristics description symbol minimum nominal maximum units notes photodiode transfer t pd 6 ? ? s vccd leading pedestal t 3p 16 ? ? s vccd trailing pedestal t 3d 16 ? ? s vccd transfer delay t d 2 ? ? s vccd transfer t v 4 ? ? s vccd rise, fall times t vr , t vf 5 ? 10 % 1, 2 fdg delay t fdg 2 ? ? s hccd delay t hs 2 ? ? s hccd transfer t e 25.0 ? ? ns shutter transfer t sub 2 ? ? s shutter delay t hd 2 ? ? s reset pulse t r 2.5 ? ? ns reset ? video delay t rv ? 2.2 ? ns h2sl ? video delay t hv ? 2.2 ? ns line time t line 77.9 ? ? s dual hccd readout 140 ? ? single hccd readout frame time t frame 129 ? ? ms quad hccd readout 257 ? ? dual hccd readout 461 ? ? single hccd readout line time (xldr bin 2x2) t line 124.9 ? ? s dual hccd readout 217.4 ? ? single hccd readout frame time (xldr bin 2x2) constant hccd timing t frame 133 ? ? ms quad hccd readout 267 ? ? dual hccd readout 466 ? ? single hccd readout frame time (xldr bin 2x2) variable hccd timing t frame 103 ? ? ms quad hccd readout 206 ? ? dual hccd readout 359 ? ? single hccd readout 1. refer to figure 41: vccd clock rise time and fall time. 2. relative to the pulse width, t v .
kai?16070 www.onsemi.com 28 timing flow charts in the timing flow charts the number of hccd clock cycles per row, nh, and the number of vccd clock cycles per frame, nv, are shown in the following table. table 21. values for nh and nv when operating the sensor in the various modes of resolution full resolution 1/4 resolution xldr nv nh nv nh nv nh quad 1650 2477 825 1238 825 1238 dual vouta, voutc 1650 4943 825 2471 825 2471 dual vouta, voutb 3278 2477 1639 1238 1639 1238 single vouta 3278 4943 1639 2471 1639 2471 1. the time to read out one line t line = line timing + nh / (pixel frequency). 2. the time to read out one frame t frame = nv ? t line + frame timing. 3. line timing: see table 23: line timing. 4. frame timing: see table 22: frame timing. 5. xldr: extended linear dynamic range. no electronic shutter in this case the photodiode exposure time is equal to the time to read out an image. this flow chart applies to both full and 1/4 resolution modes. figure 24. timing flow when electronic shutter is not used frame timing (see table 22) line timing (see table 23) pixel timing (see table 24) repeat nh times repeat nv times
kai?16070 www.onsemi.com 29 using the electronic shutter this flow chart applies to both the full and 1/4 resolution modes. the exposure time begins on the falling edge of the electronic shutter pulse on the sub pin. the exposure time ends on the falling edge of the +13 v to 0 v transition of the v1t and v1b pins. nexp is varied to change the exposure time in increments of the line time. the electronic shutter timing is obtained from figure 33. figure 25. timing flow chart using the electronic shutter for exposure control frame timing (see table 22) line timing (see table 23) pixel timing (see table 24) repeat nh times repeat nv?nexp times electronic shutter timing line timing (see table 23) pixel timing (see table 24) repeat nh times repeat nexp times note: nexp: exposure time in increments of number of lines.
kai?16070 www.onsemi.com 30 window readout using the fast dump this timing quickly dumps nv1 lines, then reads out nv2 lines, and then quickly dumps another nv3 lines. nv1 + nv2 + nv3 must be greater than or equal to nv. note when operating in quad or dual vouta + voutc modes the nv2 valid image lines must be in the center of the pixel array or contained entirely within the bottom half or top half of the pixel array. this is due to the top and bottom middle split of the vccd. in the single output or dual vouta + voutb modes the nv2 valid image lines may be located anywhere within the pixel array. the line timing with the fdgab and fdgcd pins disabled means those pins are held at a constant ?9 v. when they are enabled, they are held at +5 v during a line transfer. figure 26. sub window timing flow chart kai?16070 nv1 lines nv2 lines nv3 lines charge transfer frame timing (see table 22) line timing fdgab, fdgcd enabled (see table 23) repeat nv1 times line timing fdgab, fdgcd disabled (see table 23) pixel timing (see table 24) repeat nh times repeat nv2 times line timing fdgab, fdgcd enabled (see table 23) repeat nv3 times
kai?16070 www.onsemi.com 31 line sampling readout using the fast dump this timing repeats the process of dumping nv4 lines and reading nv5 lines. the total nv6 x (nv4 + nv5) must be greater than or equal to nv. this timing can be used for alternately skipping and reading lines. for example, if nv4 = 2 and nv5 = 1 then every third line will be read out (skip 2 read 1). figure 27. timing flow chart to alternately skip and read rows for subsampling frame timing (see table 22) line timing fdgab, fdgcd enabled (see table 23) repeat nv4 times line timing fdgab, fdgcd disabled (see table 23) pixel timing (see table 24) repeat nh times repeat nv5 times repeat nv6 times
kai?16070 www.onsemi.com 32 timing tables frame timing this timing table is for transferring charge from the photodiodes to the vccd. table 22. frame timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t f1t f1b f1t f1b f1t f1b v2t f2t f4b f2t f4b f2t f4b v3t f3t f3b f3t f3b f3t f3b v4t f4t f2b f4t f2b f4t f2b v1b f1b f1b f1b v2b f2b f2b f2b v3b f3b f3b f3b v4b f4b f4b f4b h1sa p1 p1q p1xl h1ba p1 p1q p1xl h2sa p2 p2q p2xl h2ba p2 p2q p2xl ra rhg/rlg rhgq/rlgq rxl h1sb p1 p1q p1xl h1bb p1 p2 p1 p2 p1q p2q p1q p2q p1xl p2xl p1xl p2xl h2sb p2 p2q p2xl h2bb p2 p1 p2 p1 p2q p1q p2q p1q p2xl p1xl p2xl p1xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl fdgab ?9 v ?9 v ?9 v h1sc p1 (note 1) p1q (note 1) p1xl (note 1) h1bc p1 (note 1) p1q (note 1) p1xl (note 1) h2sc p2 (note 1) p2q (note 1) p2xl (note 1) h2bc p2 (note 1) p2q (note 1) p2xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1 (note 1) p1q (note 1) p1xl (note 1) h1bd p1 p2 (note 1) p1q p2q (note 1) p1xl p2xl (note 1) h2sd p2 (note 1) p2q (note 1) p2xl (note 1) h2bd p2 p1 (note 1) p2q p1q (note 1) p2xl p1xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) fdgcd ?9 v ?9 v ?9 v shp shp1 shpq (note 4) shd shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. this note left intentionally empty. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?16070 www.onsemi.com 33 line timing this timing is for transferring one line of charge from the vccd to the hccd. table 23. line timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t l1t l1b 2 l1t 2 l1b 2 l1t 2 l1b v2t l2t l4b 2 l2t 2 l4b 2 l2t 2 l4b v3t l3t l3b 2 l3t 2 l3b 2 l3t 2 l3b v4t l4t l2b 2 l4t 2 l2b 2 l4t 2 l2b v1b l1b 2 l1b 2 l1b v2b l2b 2 l2b 2 l2b v3b l3b 2 l3b 2 l3b v4b l4b 2 l4b 2 l4b h1sa p1l p1lq p3xl h1ba p1l p1lq p3xl h2sa p2l p2lq p4xl h2ba p2l p2lq p4xl ra rhg/rlg rhgq/rlgq rxl h1sb p1l p1lq p3xl h1bb p1l p2l p1l p2l p1lq p2lq p1lq p2lq p3xl p4xl p3xl p4xl h2sb p2l p2lq p4xl h2bb p2l p1l p2l p1l p2lq p1lq p2lq p1lq p4xl p3xl p4xl p3xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl fdgab ?9 v ?9 v ?9 v h1sc p1l (note 1) p1lq (note 1) p3xl (note 1) h1bc p1l (note 1) p1lq (note 1) p3xl (note 1) h2sc p2l (note 1) p2lq (note 1) p4xl (note 1) h2bc p2l (note 1) p2lq (note 1) p4xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1l (note 1) p1lq (note 1) p3xl (note 1) h1bd p1l p2l (note 1) p1lq p2lq (note 1) p3xl p4xl (note 1) h2sd p2l (note 1) p2lq (note 1) p4xl (note 1) h2bd p2l p1l (note 1) p2lq p1lq (note 1) p4xl p3xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) fdgcd ?9 v ?9 v ?9 v shp shp1 shpq (note 4) shd shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. the notation 2 l1b means repeat the l1b timing twice for every line. this sums two rows into the hccd. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?16070 www.onsemi.com 34 pixel timing this timing is for transferring one pixel from the hccd to the output amplifier. table 24. pixel timing device pin full resolution, high gain or low gain 1/4 resolution, high gain or low gain 1/4 resolution xldr quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta quad dual vouta voutc dual vouta voutb single vouta v1t ?9 v ?9 v ?9 v v2t ?9 v ?9 v ?9 v v3t 0v 0v 0v v4t 0v 0v 0v v1b ?9 v ?9 v ?9 v v2b 0v 0v 0v v3b 0v 0v 0v v4b ?9 v ?9 v ?9 v h1sa p1 p1q p1xl h1ba p1 p1q p1xl h2sa p2 p2q p2xl h2ba p2 p2q p2xl ra rhg/rlg rhgq/rlgq rxl h1sb p1 p1q p1xl h1bb p1 p2 p1 p2 p1q p2q p1q p2q p1xl p2xl p1xl p2xl h2sb p2 p2q p2xl h2bb p2 p1 p2 p1 p2q p1q p2q p1q p2xl p1xl p2xl p1xl rb rhg/ rlg (note 1) rhg/ rlg (note 1) rhgq/ rlgq (note 1) rhgq/ rlgq (note 1) rxl (note 1) rxl (note 1) r2ab r2hg/r2lg r2hgq/r2lgq r2xl r2ab ?9 v ?9 v ?9 v h1sc p1 (note 1) p1q (note 1) p1xl (note 1) h1bc p1 (note 1) p1q (note 1) p1xl (note 1) h2sc p2 (note 1) p2q (note 1) p2xl (note 1) h2bc p2 (note 1) p2q (note 1) p2xl (note 1) rc rhg/rlg (note 1) rhgq/rlgq (note 1) rxl (note 1) h1sd p1 (note 1) p1q (note 1) p1xl (note 1) h1bd p1 p2 (note 1) p1q p2q (note 1) p1xl p2xl (note 1) h2sd p2 (note 1) p2q (note 1) p2xl (note 1) h2bd p2 p1 (note 1) p2q p1q (note 1) p2xl p1xl (note 1) rd rhg/ rlg (note 1) (note 1) rhgq/ rlgq (note 1) (note 1) rxl (note 1) (note 1) r2cd r2hg/r2lg (note 1) r2hgq/r2lgq (note 1) r2xl (note 1) r2ab ?9 v ?9 v ?9 v shp (note 2) shp1 shpq (note 4) shd (note 2) shd1 shdq (note 5) 1. this clock should be held at its high level voltage (0 v) or held at +5.0 v for compatibility with truesense 5.5 micron interli ne transfer ccd family of products. 2. shp and shd are the sample clocks for the analog front end (afe) signal processor. 3. this note intentionally left empty. 4. use shplg for the afe processing the low gain signal. use shphg for the afe processing the high gain signal. 5. use shdlg for the afe processing the low gain signal. use shdhg for the afe processing the high gain signal.
kai?16070 www.onsemi.com 35 timing diagrams frame timingdiagrams figure 28. frame timing diagram note: see table 22 for pin assignments. the charge in the photodiodes begins its transfer to the vccd on the rising edge of the +13 v pulse and is completed by the falling edge of the +13 v pulse on f1t and f1b. during the time period when f1t and f1b are at +13 v antiblooming protection is disabled. the photodiode integration time ends on the falling edge of the +13 v pulse.
kai?16070 www.onsemi.com 36 line timing diagrams figure 29. line timing diagram note: see table 23 for device pin assignments. if the line is to be dumped then clock the fdgab and fdgcd pins as shown. this dumping process eliminates a line of charge and the hccd does not have to be clocked. to transfer a line from the vccd to the hccd without dumping the charge, hold the fdgab and fdgcd pins at a constant ?9 v. figure 30. fast dump gate timing detail a note: see table 23 for device pin assignments. l4b, l1t fdgab, fdgcd l1b, l2t 4tv detail a when the vccd is clocked while the fdgab and fdgcd pins are at +5 v, charge is diverted to a drain instead of transferring to the hccd. the fdg pins must be at +5 v before the first vccd timing edge begins its transition. the fdg pin must not begin its transition from +5 v back to ?9 v until the last vccd timing edge has completed its transition.
kai?16070 www.onsemi.com 37 figure 31. 1/4 resolution line timing diagram note: see table 23 center column for pin assignments. rhgq p2lq p1lq p1q time duration is 8tv ?2 v +3 v ?4.4 v 0 v this extra clock cycle is important! p2q p1q p2q 1/4 resolution line timing the hccd 1/4 resolution timing has one hccd clock cycle added. this does a one pixel shift of the hccd before the 2? pixel char ge summing starts on the output amplifier. the one pixel shift is necessary because of the odd number (11 pixels) of dummy pixels at the start of the hccd. without the one pixel shift the last dark reference columns would be summed with the first photoactive column instead of adding together the first two photoactive columns. figure 32. xldr line timing diagram note: see table 23 right columns for pin assignments. rxl p4xl p3xl p2xl p1xl p2xl p1xl time duration is 8tv ?2 v +3 v ?4.4 v 0 v this extra clock cycle is important! xldr line timing like the 1/4 resolution mode, the xldr timing also sums two pixels on the output amplifier sense node. therefore it also requires one hccd clock cycle within the line timing.
kai?16070 www.onsemi.com 38 electronic shutter timing diagram figure 33. electronic shutter timing diagram t v 2 sub vab ves 0 v ?9 v vccd clock t sub t v 2 the electronic shutter pulse can be inserted at the end of any line of the hccd timing. the hccd should be empty when the electronic shutter is pulsed. a recommended position for the electronic shutter is just after the last pixel is read out of a line. the vccd clocks should not resume until at least t v /2 s after the electronic shutter pulse has finished. the hccd clocks can be run during the electronic shutter pulse as long as the hccd does not contain valid image data. for short exposures less than one line time, the electronic shutter pulse can appear inside the frame timing diagram of figure 28. any electronic shutter pulse transition should be t v /2 away from any vccd clock transition.
kai?16070 www.onsemi.com 39 pixel timing diagrams figure 34. high gain pixel timing video r2hg rhg shp1 shd1 p2 p1 high gain pixel timing te ?4.4 v 0 v ?4.4 v 0 v ?2 v +3 v ?2 v +3 v note: see table 24 left columns for pin assignments. use this pixel timing to read out every pixel at high gain. if the sensor is to be permanently operated at high gain, the r2ab and r2cd pins can be left floating or set to any dc voltage between +3 v and +5 v. they are internally biased to +4.3 v. the shp1 and shd1 pulses indicate where the camera electronics should sample the video waveform. the shp1 and shd1 pulses are not applied to the image sensor.
kai?16070 www.onsemi.com 40 figure 35. low gain pixel timing note: see table 24 left columns for pin assignments. video r2lg rlg shp1 shd1 p2 p1 low gain pixel timing te ?4.4 v 0 v ?4.4 v 0 v ?2 v +3 v ?2 v +3 v use this timing to read out every pixel at low gain. if the sensor is to be permanently operated at low gain, the ra, rb, rc, and rd pins can be set to any dc voltage between +3 v and +5 v. the shp1 and shd1 pulses indicate where the camera electronics should sample the video waveform. the shp1 and shd1 pulses are not applied to the image sensor.
kai?16070 www.onsemi.com 41 figure 36. 1/4 resolution high gain pixel timing note: see table 24 center columns for pin assignments. video r2hgq rhgq shpq shdq p2q p1q 1/4 resolution high gain pixel timing te ?4.4 v 0 v ?4.4 v 0 v ?2 v +3 v ?2 v +3 v use this pixel timing to read out every pixel at high gain. if the sensor is to be permanently operated at high gain, the r2ab and r2cd pins can be left floating or set to any dc voltage between +3 v and +5 v. they are internally biased to +4.3 v. the shpq and shdq pulses indicate where the camera electronics should sample the video waveform. the shpq and shdq pulses are not applied to the image sensor. the ra, rb, rc, and rd pins are pulsed at half the frequency of the hccd clocks. this causes two pixels to be summed on the output amplifier sense node. the shpq and shdq clocks are also half the frequency of the hccd clocks.
kai?16070 www.onsemi.com 42 figure 37. 1/4 resolution low gain pixel timing note: see table 24 center columns for pin assignments. video r2hgq rhgq shpq shdq p2q p1q te ?4.4 v 0 v ?4.4 v 0 v ?2 v +3 v ?2 v +3 v 1/4 resolution low gain pixel timing use this timing to read out every pixel at low gain. if the sensor is to be permanently operated at low gain, the ra, rb, rc, and rd pins can be set to any dc voltage between +3 v and +5 v. the shpq and shdq pulses indicate where the camera electronics should sample the video waveform. the shpq and shdq pulses are not applied to the image sensor. the r2ab, and r2cd pins are pulsed at half the frequency of the hccd clocks. this causes two pixels to be summed on the output amplifier sense node. the shpq and shdq clocks are also half the frequency of the hccd clocks.
kai?16070 www.onsemi.com 43 figure 38. xldr timing with constant hccd. operating at 20 mhz note: see table 24 right columns for pin assignments. figure 39. xldr timing with variable hccd clocking note: see table 24 right columns for pin assignments. use this pixel timing to operate the image sensor in the extended linear dynamic range mode (xldr). this mode requires two sets of analog front end (afe) signal processing electronics for each output. as shown in figure 39, one afe samples the pixel at low gain (shplg and shdlg) and the other afe samples the pixel at high gain (shphg and shdhg).
kai?16070 www.onsemi.com 44 two hccd pixels are summed on the output amplifier to obtain enough charge to fully use the 82 db dynamic range of the xldr timing. combined with two?line vccd summing, a total of 160,000 electrons of signal (4x 40,000) can be sampled with 12 electrons or less noise. 82 db linear dynamic range is very large. make certain the camera optics is capable of focusing an 82 db dynamic range image on the sensor. lens flare caused by inexpensive optics or even dust on the lens will limit the dynamic range. this timing shows the hccd in figure 39, not being clocked at a constant frequency. if this is a problem for the hccd timing generator , then the hccd may be clocked at a constant frequency at the expense of about 33% slower frame rate. figure 40. block diagram showing the afe connections for xldr timing low gain afe high gain afe sensor output shpl g shdl g shphg shdhg low gain digital out high gain digital out caution : in the xdr mode this output of the ccd can produce large signals that may damage some afe devices and should be electrically attenuated! vccd clock rise and fall time figure 41. vccd clock rise time and fall time 90% 10% t vf t vr t v t v t vf t vr
kai?16070 www.onsemi.com 45 mechanical information completed assembly figure 42. completed assembly of sealed cover glass configuration (1 of 2) notes: 1. see ordering information for marking code. 2. cover glass not to overhang package holes or outer ceramic edges. 3. glass epoxy not to extend over image array. 4. no materials to interfere with clearance through package holes. 5. units: in [mm]
kai?16070 www.onsemi.com 46 figure 43. completed assembly of sealed cover glass configuration (2 of 2) notes: 1. units in [mm] figure 44. completed assembly view of taped cover glass configuration shown with taped?on cover glass
kai?16070 www.onsemi.com 47 cover glass, ar coated, 2 sides figure 45. cover glass, ar coated, 2 sides notes: 1. substrate = schott d263t eco 2. dust, scratch, inclusion specification: a.) 20 m max size in zone a b.) zone a = 1.474 x 1.000 [16.43 x 10.08] centered 3. mar coated both sides 4. spectral transmission a.) 350 ? 365 nm: t 88% b.) 365 ? 405 nm: t 94% c.) 405 ? 450 nm: t 98% d.) 450 ? 650 nm: t 99% e.) 650 ? 690 nm: t 98% f.) 690 ? 770 nm: t 94% g.) 770 ? 870 nm: t 88% 5. units: in [mm]
kai?16070 www.onsemi.com 48 cover glass, clear no coatings (taped) figure 46. cover glass, clear no coatings (taped) notes: 1. substrate = schott d263t eco 2. dust, scratch, inclusion specification: none 3. no optical coatings on this glass 4. units: mm
kai?16070 www.onsemi.com 49 cover glass transmission figure 47. cover glass transmission for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com . on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular pu rpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulatio ns and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semicond uctor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typicals? mus t be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconduc tor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or si milar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, cost s, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer . this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kai?16070/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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